In order to ensure the correct order of reading the registers isn't it sufficient to use the following:
return ADCL | (ADCH << 8);
This eliminates two uint vars and two stores and two reads in wiring_analog.c
#if defined(ADCSRA) && defined(ADCL)
...
// low = ADCL;
// high = ADCH;
// return (high << 8) | low;
return (ADCL | ADCH<<8);
#else
// we dont have an ADC, return 0
// low = 0;
// high = 0;
return(0);
#endif
Is there some compiler optimisation that could mess that up ?
// without a delay, we seem to read from the wrong channel
delay(1);
Huh? That's already five times slower than sleeping the chip for the full conversion time.
Datasheet says changing Mux after starting a conversion will only take effect for the next conversion, which seems logical. I dont see how else it can get the "wrong" channel.
:~